SUGGESTED FIX
Webrev: http://analemma.sfbay.sun.com/net/prt-archiver.sfbay/data/archived_workspaces/main/c2_baseline/2005/20050329164723.kvn.6239807/workspace/webrevs/webrev-2005.03.29/index.html
Check the result of CPUID instruction for AMD features
(the code was taken from the amd64 port).
Use this information to generate correspondent most efficient
heap allocation prefetch instruction on x86:
Pentium 3 - prefetcht2 128
Pentium 4 - prefetchnta 512
Athlon - prefetchw 128
Opteron - prefetchw 386
And don't generate any prefetching instructions when SSE or 3DNow
are not supported (after the fix for 6229114 we are generating
CMP EAX,(mem+dist) which could reference outside a heap).
Add check for SSE3 (change 'UseSSE==2' to 'UseSSE>=2').
It is only check - the preparation for the future use of
SSE3 instructions.
Note: I also did the experiment with GC prefetching but didn't
see improvement since you have to generate the sse check
in addition to a prefetch instruction.
###@###.### 2005-04-01 00:06:16 GMT
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