EVALUATION

@brackeen: Well the only thing I can think of (for x86) is to use partial register moves (using MOVZX instructions instead of SHR-AND sequences), e.g.:

  int g = (anInt >> 8) & 0xff;

  MOV    EBX,ECX
  SHR    EBX,#8
  AND    EBX,#255

vs.

  MOVZX8 EBX,CH

or:

  int b = anInt & 0xff;

  MOV    EBX,ECX
  AND    EBX,#255

vs.

  MOVZX8 EBX,CL

While the latter one is likely to have the same performance, as the resulting micro instructions should be the same.  I will run some tests.  Do you have a use-case you can send me?
                                     

EVALUATION

http://hg.openjdk.java.net/jdk7/hotspot-comp/hotspot/rev/337400e7a5dd
                                     

PUBLIC COMMENTS

Please note that SPARC has signed loads (which sign-extend into the 64-bit
integer registers) for byte, short, and int.  They are: LDSB, LDSH, LDSW.
SPARC also has unsigned loads (which zero-extend): LDUB, LDUH, LDUW.
Of course, SPARC also has a 64-bit load: LDX.
                                     

PUBLIC COMMENTS

All these instructions are used in my changes.
                                     

EVALUATION

Some micro benchmarks show a big performance win.
                                     

PUBLIC COMMENTS

I have to revert that.  On 32-bit x86 the LoadUI2L opcode helps a lot.
                                     

PUBLIC COMMENTS

While implementing LoadUI2L I noticed that it does not make much sense to add that one.

On x86_64 there is no such instruction to do that load, because loading an E-register clears the high bits implicitly anyway.  And on SPARC all integer loads are unsigned integer loads.