When DecodeN instruction does not fold into address expression (Sparc) it may prevent implicit null check generation if it scheduled below the null check since the corresponding memory instruction could not be moved (first case):
064 B5: # B26 B6 <- B4 Freq: 0.858868
064 + LDUW [R_I0 + #16],R_L1 ! int ! Field java/lang/String.offset
068 + LDUW [R_I0 + #12],R_I0 ! compressed ptr ! Field java/lang/String.value
06c + LDUW [R_I1 + #16],R_L7 ! int ! Field java/lang/String.offset
070 + CMP R_I0,narrowoop: NULL ! compressed ptr
074 LDUW [R_I1 + #12],R_I1 ! compressed ptr ! Field java/lang/String.value
078 BPeq ccr,B26 P=0.000001 C=-1.000000
078 ADD R_L1,R_I2,R_L1
078
080 B6: # B26 B7 <- B5 Freq: 0.858867
080 + decode_heap_oop_not_null R_I0, R_G1
088 + ADD R_L1,R_L2,R_L4
08c ADD R_L7,R_L2,R_L5
090 LDUW [R_G1 + #12],R_L3 ! range
094 + ADD R_L4,#-1,R_G3
098 decode_heap_oop_not_null R_I1, R_G5
0a0 + CMP R_L1,R_L3 ! unsigned
0a4 BPuge icc_U,B26 P=0.000001 C=-1.000000
0a4 ADD R_L5,#-1,R_G4
0a4
0ac B7: # B26 B8 <- B6 Freq: 0.858866
0ac + CMP R_G3,R_L3 ! unsigned
0b0 BPuge icc_U,B26 P=0.000001 C=-1.000000
0b0
0b8 B8: # B26 B9 <- B7 Freq: 0.858865
0b8 LDUW [R_G5 + #12],R_L0 ! range
0bc NullCheck R_G5
0bc
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Java